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174
common/emitter/internal.h
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174
common/emitter/internal.h
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// SPDX-FileCopyrightText: 2002-2025 PCSX2 Dev Team
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// SPDX-License-Identifier: GPL-3.0+
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#pragma once
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#include "common/emitter/x86types.h"
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#include "common/emitter/instructions.h"
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namespace x86Emitter
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{
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#define OpWriteSSE(pre, op) xOpWrite0F(pre, op, to, from)
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extern void SimdPrefix(u8 prefix, u16 opcode);
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extern void EmitSibMagic(uint regfield, const void* address, int extraRIPOffset = 0);
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extern void EmitSibMagic(uint regfield, const xIndirectVoid& info, int extraRIPOffset = 0);
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extern void EmitSibMagic(uint reg1, const xRegisterBase& reg2, int = 0);
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extern void EmitSibMagic(const xRegisterBase& reg1, const xRegisterBase& reg2, int = 0);
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extern void EmitSibMagic(const xRegisterBase& reg1, const void* src, int extraRIPOffset = 0);
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extern void EmitSibMagic(const xRegisterBase& reg1, const xIndirectVoid& sib, int extraRIPOffset = 0);
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extern void EmitRex(uint regfield, const void* address);
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extern void EmitRex(uint regfield, const xIndirectVoid& info);
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extern void EmitRex(uint reg1, const xRegisterBase& reg2);
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extern void EmitRex(const xRegisterBase& reg1, const xRegisterBase& reg2);
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extern void EmitRex(const xRegisterBase& reg1, const void* src);
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extern void EmitRex(const xRegisterBase& reg1, const xIndirectVoid& sib);
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extern void _xMovRtoR(const xRegisterInt& to, const xRegisterInt& from);
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template <typename T>
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inline void xWrite(T val)
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{
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*(T*)x86Ptr = val;
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x86Ptr += sizeof(T);
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}
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template <typename T1, typename T2>
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__emitinline void xOpWrite(u8 prefix, u8 opcode, const T1& param1, const T2& param2, int extraRIPOffset = 0)
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{
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if (prefix != 0)
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xWrite8(prefix);
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EmitRex(param1, param2);
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xWrite8(opcode);
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EmitSibMagic(param1, param2, extraRIPOffset);
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}
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template <typename T1, typename T2>
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__emitinline void xOpAccWrite(u8 prefix, u8 opcode, const T1& param1, const T2& param2)
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{
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if (prefix != 0)
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xWrite8(prefix);
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EmitRex(param1, param2);
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xWrite8(opcode);
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}
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//////////////////////////////////////////////////////////////////////////////////////////
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// emitter helpers for xmm instruction with prefixes, most of which are using
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// the basic opcode format (items inside braces denote optional or conditional
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// emission):
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//
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// [Prefix] / 0x0f / [OpcodePrefix] / Opcode / ModRM+[SibSB]
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//
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// Prefixes are typically 0x66, 0xf2, or 0xf3. OpcodePrefixes are either 0x38 or
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// 0x3a [and other value will result in assertion failue].
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//
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template <typename T1, typename T2>
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__emitinline void xOpWrite0F(u8 prefix, u16 opcode, const T1& param1, const T2& param2)
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{
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if (prefix != 0)
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xWrite8(prefix);
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EmitRex(param1, param2);
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SimdPrefix(0, opcode);
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EmitSibMagic(param1, param2);
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}
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template <typename T1, typename T2>
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__emitinline void xOpWrite0F(u8 prefix, u16 opcode, const T1& param1, const T2& param2, u8 imm8)
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{
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if (prefix != 0)
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xWrite8(prefix);
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EmitRex(param1, param2);
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SimdPrefix(0, opcode);
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EmitSibMagic(param1, param2, 1);
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xWrite8(imm8);
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}
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template <typename T1, typename T2>
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__emitinline void xOpWrite0F(u16 opcode, const T1& param1, const T2& param2)
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{
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xOpWrite0F(0, opcode, param1, param2);
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}
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template <typename T1, typename T2>
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__emitinline void xOpWrite0F(u16 opcode, const T1& param1, const T2& param2, u8 imm8)
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{
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xOpWrite0F(0, opcode, param1, param2, imm8);
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}
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// VEX 2 Bytes Prefix
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template <typename T1, typename T2, typename T3>
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__emitinline void xOpWriteC5(u8 prefix, u8 opcode, const T1& param1, const T2& param2, const T3& param3)
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{
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pxAssert(prefix == 0 || prefix == 0x66 || prefix == 0xF3 || prefix == 0xF2);
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const xRegisterBase& reg = param1.IsReg() ? param1 : param2;
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u8 nR = reg.IsExtended() ? 0x00 : 0x80;
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u8 L;
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// Needed for 256-bit movemask.
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if constexpr (std::is_same_v<T3, xRegisterSSE>)
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L = param3.IsWideSIMD() ? 4 : 0;
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else
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L = reg.IsWideSIMD() ? 4 : 0;
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u8 nv = (param2.IsEmpty() ? 0xF : ((~param2.GetId() & 0xF))) << 3;
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u8 p =
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prefix == 0xF2 ? 3 :
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prefix == 0xF3 ? 2 :
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prefix == 0x66 ? 1 :
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0;
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xWrite8(0xC5);
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xWrite8(nR | nv | L | p);
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xWrite8(opcode);
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EmitSibMagic(param1, param3);
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}
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// VEX 3 Bytes Prefix
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template <typename T1, typename T2, typename T3>
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__emitinline void xOpWriteC4(u8 prefix, u8 mb_prefix, u8 opcode, const T1& param1, const T2& param2, const T3& param3, int w = -1)
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{
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pxAssert(prefix == 0 || prefix == 0x66 || prefix == 0xF3 || prefix == 0xF2);
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pxAssert(mb_prefix == 0x0F || mb_prefix == 0x38 || mb_prefix == 0x3A);
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const xRegisterInt& reg = param1.IsReg() ? param1 : param2;
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u8 nR = reg.IsExtended() ? 0x00 : 0x80;
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u8 nB = param3.IsExtended() ? 0x00 : 0x20;
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u8 nX = 0x40; // likely unused so hardwired to disabled
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u8 L = reg.IsWideSIMD() ? 4 : 0;
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u8 W = (w == -1) ? (reg.GetOperandSize() == 8 ? 0x80 : 0) : // autodetect the size
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0x80 * w; // take directly the W value
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u8 nv = (~param2.GetId() & 0xF) << 3;
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u8 p =
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prefix == 0xF2 ? 3 :
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prefix == 0xF3 ? 2 :
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prefix == 0x66 ? 1 :
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0;
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u8 m =
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mb_prefix == 0x3A ? 3 :
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mb_prefix == 0x38 ? 2 :
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1;
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xWrite8(0xC4);
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xWrite8(nR | nX | nB | m);
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xWrite8(W | nv | L | p);
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xWrite8(opcode);
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EmitSibMagic(param1, param3);
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}
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} // namespace x86Emitter
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